diff options
| -rw-r--r-- | target/linux/realtek/files-6.12/drivers/net/dsa/rtl83xx/dsa.c | 37 |
1 files changed, 28 insertions, 9 deletions
diff --git a/target/linux/realtek/files-6.12/drivers/net/dsa/rtl83xx/dsa.c b/target/linux/realtek/files-6.12/drivers/net/dsa/rtl83xx/dsa.c index a84d1be6d6..38608734f3 100644 --- a/target/linux/realtek/files-6.12/drivers/net/dsa/rtl83xx/dsa.c +++ b/target/linux/realtek/files-6.12/drivers/net/dsa/rtl83xx/dsa.c @@ -613,25 +613,44 @@ static void rtl83xx_config_interface(int port, phy_interface_t interface) pr_debug("configured port %d for interface %s\n", port, phy_modes(interface)); } -static void rtldsa_phylink_get_caps(struct dsa_switch *ds, int port, +static void rtldsa_83xx_phylink_get_caps(struct dsa_switch *ds, int port, struct phylink_config *config) { /* - * TODO: This capability check will need some love. Depending on the model and the - * port different MAC features and link modes are supported. For now just enable all - * required MAC and PHY capabilites so that we can make use of the ports. + * TODO: This needs to take into account the MAC to SERDES mapping and the + * specific SoC capabilities. Right now we just assume all RTL83xx ports + * support up to 1G standalone and QSGMII as that covers most real-world + * use cases. */ + config->mac_capabilities = MAC_ASYM_PAUSE | MAC_SYM_PAUSE | MAC_10 | MAC_100 | + MAC_1000FD; + __set_bit(PHY_INTERFACE_MODE_1000BASEX, config->supported_interfaces); + __set_bit(PHY_INTERFACE_MODE_GMII, config->supported_interfaces); + __set_bit(PHY_INTERFACE_MODE_INTERNAL, config->supported_interfaces); + __set_bit(PHY_INTERFACE_MODE_SGMII, config->supported_interfaces); + __set_bit(PHY_INTERFACE_MODE_QSGMII, config->supported_interfaces); +} + +static void rtldsa_93xx_phylink_get_caps(struct dsa_switch *ds, int port, + struct phylink_config *config) +{ + /* + * TODO: This needs to take into account the MAC to SERDES mapping and the + * specific SoC capabilities. Right now we just assume all RTL93xx ports + * support up to 10G standalone and up to USXGMII as that covers most + * real-world use cases. + */ config->mac_capabilities = MAC_ASYM_PAUSE | MAC_SYM_PAUSE | MAC_10 | MAC_100 | MAC_1000FD | MAC_2500FD | MAC_5000FD | MAC_10000FD; __set_bit(PHY_INTERFACE_MODE_1000BASEX, config->supported_interfaces); - __set_bit(PHY_INTERFACE_MODE_10GBASER, config->supported_interfaces); - __set_bit(PHY_INTERFACE_MODE_2500BASEX, config->supported_interfaces); __set_bit(PHY_INTERFACE_MODE_GMII, config->supported_interfaces); __set_bit(PHY_INTERFACE_MODE_INTERNAL, config->supported_interfaces); - __set_bit(PHY_INTERFACE_MODE_QSGMII, config->supported_interfaces); __set_bit(PHY_INTERFACE_MODE_SGMII, config->supported_interfaces); + __set_bit(PHY_INTERFACE_MODE_QSGMII, config->supported_interfaces); + __set_bit(PHY_INTERFACE_MODE_10GBASER, config->supported_interfaces); + __set_bit(PHY_INTERFACE_MODE_2500BASEX, config->supported_interfaces); __set_bit(PHY_INTERFACE_MODE_USXGMII, config->supported_interfaces); } @@ -2562,7 +2581,7 @@ const struct dsa_switch_ops rtl83xx_switch_ops = { .phy_read = rtldsa_phy_read, .phy_write = rtldsa_phy_write, - .phylink_get_caps = rtldsa_phylink_get_caps, + .phylink_get_caps = rtldsa_83xx_phylink_get_caps, .phylink_mac_config = rtl83xx_phylink_mac_config, .phylink_mac_link_down = rtl83xx_phylink_mac_link_down, .phylink_mac_link_up = rtl83xx_phylink_mac_link_up, @@ -2619,7 +2638,7 @@ const struct dsa_switch_ops rtl93xx_switch_ops = { .phy_read = rtldsa_phy_read, .phy_write = rtldsa_phy_write, - .phylink_get_caps = rtldsa_phylink_get_caps, + .phylink_get_caps = rtldsa_93xx_phylink_get_caps, .phylink_mac_config = rtl93xx_phylink_mac_config, .phylink_mac_link_down = rtl93xx_phylink_mac_link_down, .phylink_mac_link_up = rtl93xx_phylink_mac_link_up, |